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Final Electrical Specifications
LT1469 Dual 90MHz, 22V/s 16-Bit Accurate Operational Amplifier
February 2000
FEATURES
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DESCRIPTIO
90MHz Gain Bandwidth, f = 100kHz Maximum Input Offset Voltage: 125V Settling Time: 900ns (AV = -1, 150V, 10V Step) 22V/s Slew Rate Low Distortion: -96.5dB for 100kHz, 10VP-P Maximum Input Offset Voltage Drift: 3V/C Maximum Inverting Input Bias Current: 10nA Minimum DC Gain: 300V/mV Minimum Output Swing into 2k: 12.8V Unity-Gain Stable Input Noise Voltage: 5nV/Hz Input Noise Current: 0.6pA/Hz Total Input Noise Optimized for 1k < RS < 20k Specified at 5V and 15V Supplies
The LT(R)1469 is a dual, precision high speed operational amplifier with 16-bit accuracy and 900ns settling to 150V for 10V signals. This unique blend of precision and AC performance makes the LT1469 the optimum choice for high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. The 90MHz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC accuracy allow full 16-bit AC and DC performance. The 22V/s slew rate of the LT1469 improves large signal performance compared to other precision op amps in applications such as active filters and instrumentation amplifiers. The LT1469 is manufactured on Linear Technology's complementary bipolar process and is available in 8-pin PDIP and SO packages. A single version,the LT1468, is also available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s s
Precision Instrumentation High Accuracy Data Acquisition Systems 16-Bit DAC Current-to-Voltage Converter ADC Buffer Low Distortion Active Filters Photodiode Amplifiers
TYPICAL APPLICATIO
16-Bit Accurate Single Ended to Differential ADC Buffer +
1/2 LT1469
200
-
VIN 10pF 2k -IN 2k 300pF
1469 TA01
300pF +IN LTC1604 16 BITS 333ksps
-
1/2 LT1469
200
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1469
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW OUT A 1 -IN A 2 A +IN A 3 V- 4 B 5 6 -IN B +IN B 8 7 V+ OUT B
Total Supply Voltage (V + to V -) .............................. 36V Input Current (Note 2) ........................................ 10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) .. - 40C to 85C Specified Temperature Range (Note 5) ... - 40C to 85C Maximum Junction Temperature .......................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1469CS8 LT1469IS8 LT1469CN8 LT1469IN8 S8 PART MARKING 1469 1469I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 130C/W (N8) TJMAX = 150C, JA = 190C/W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VOS IOS IB - IB + en in RIN CIN VCM Input Offset Voltage Input Offset Current Inverting Input Bias Current Noninverting Input Bias Current Input Noise Voltage Density Input Noise Current Density Input Resistance Input Capacitance Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR Common Mode Rejection Ratio Minimum Supply Voltage PSRR AVOL Power Supply Rejection Ratio Large-Signal Voltage Gain VCM = 12.5V VCM = 2.5V f = 10kHz f = 10kHz VCM = 12.5V Differential CONDITIONS
TA = 25C, VCM = 0V unless otherwise noted.
VSUPPLY 15V 5V 5V to 15V 5V to 15V 5V to 15V 5V to 15V 5V to 15V 15V 15V 15V 15V 5V 15V 5V 15V 5V 96 96 100 15V 15V 5V 5V 15V 15V 5V 5V 15V 5V 15V 300 300 200 200 13 12.8 3 2.8 15 15 25 12.5 2.5 100 50 MIN TYP 30 50 13 3 -10 5 0.6 240 150 4 13.5 3.5 -14.3 -4.3 110 112 2.5 112 9000 5000 6000 3000 13.6 13.5 3.6 3.5 22 22 40 4.5 -12.5 -2.5 MAX 125 200 50 10 40 UNITS V V nA nA nA nV/Hz pA/Hz M k pF V V V V dB dB V dB V/mV V/mV V/mV V/mV V V V V mA mA mA
Guaranteed by PSRR VS = 4.5V to 15V VOUT = 12.5V, RL = 10k VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 10k VOUT = 2.5V, RL = 2k RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive VOUT = 12.5V, 1mV Overdrive VOUT = 2.5V, 1mV Overdrive VOUT = 0V, 0.2V Overdrive (Note 3)
VOUT
Maximum Output Swing
IOUT ISC
Maximum Output Current Output Short-Circuit Current
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LT1469
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER SR FPBW GBW tr, tf OS tPD tS Slew Rate Full-Power Bandwidth Gain Bandwidth Product Rise Time, Fall Time Overshoot Propagation Delay Settling Time CONDITIONS
TA = 25C, VCM = 0V unless otherwise noted.
VSUPPLY 15V 5V 15V 5V 15V 5V 15V 5V 15V 5V 15V 5V 15V 15V 5V 15V 15V 15V 5V 15V 5V 15V 5V 5V to 15V 5V to 15V 100 100 60 55 MIN 15 11 TYP 22 17 350 900 90 88 11 12 30 35 9 10 760 900 770 - 96.5 0.02 120 120 4.1 3.8 5.2 5 225 350 18 78 93 93 97 MAX UNITS V/s V/s kHz kHz MHz MHz ns ns % % ns ns ns ns ns dB dB dB mA mA V V nA nA dB dB dB
AV = -10, RL = 2k (Note 6) 10V Peak, (Note 7) 3V Peak, (Note 7) f = 100kHz, RL = 2k AV = 1, 10% to 90%, 0.1V AV = 1, 0.1V AV = 1, 50% VIN to 50% VOUT, 0.1V 10V Step, 0.01%, AV = -1 10V Step, 150V, AV = -1 5V Step, 0.01%, AV = -1 AV = 1, 10VP-P, 100kHz AV = 1, f = 100kHz VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 2k Per Amplifier
THD ROUT
Total Harmonic Distortion Output Resistance Channel Separation
IS VOS IB- IB+ CMRR PSRR
Supply Current Input Offset Voltage Match Inverting Input Bias Current Match Noninverting Input Bias Current Match Common Mode Rejection Match Power Supply Rejection Match
VCM = 12.5V (Note 9) VCM = 2.5V (Note 9) VS = 4.5V to 15V (Note 9)
15V 5V
The q denotes the specifications which apply over the temperature range 0C TA 70C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER VOS VOS/T IOS IOS/T IB - IB -/T IB + VCM Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Offset Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Noninverting Input Bias Current Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR Common Mode Rejection Ratio VCM = 12.5V VCM = 2.5V (Note 8) (Note 8) (Note 8) CONDITIONS VSUPPLY 15V 5V
q q
MIN
TYP
MAX 350 350
UNITS V V V/C nA pA/C nA pA/C nA V V
5V to 15V q 5V to 15V q 5V to 15V q 5V to 15V q 5V to 15V 15V 5V 15V 5V 15V 5V
q
1 60
3 80 20
40 60 12.5 2.5 -12.5 -2.5 94 94
5V to 15V q
q q q q q q
V V dB dB
3
LT1469
0C TA 70C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER Minimum Supply Voltage PSRR AVOL Power Supply Rejection Ratio Large-Signal Voltage Gain
ELECTRICAL CHARACTERISTICS
CONDITIONS
The q denotes the specifications which apply over the temperature range
VSUPPLY
q q
MIN 95 100 100 100 100 12.9 12.7 2.9 2.7 12.5 12.5 17 13 9 55 50 98 98
TYP
MAX 4.5
UNITS V dB V/mV V/mV V/mV V/mV V V V V mA mA mA V/s V/s MHz MHz dB dB
Guaranteed by PSRR VS = 4.5V to 15V VOUT = 12.5V, RL = 10k VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 10k VOUT = 2.5V, RL = 2k RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive VOUT = 12.5V, 1mV Overdrive VOUT = 2.5V, 1mV Overdrive VOUT = 0V, 0.2V Overdrive (Note 3) AV = -10, RL = 2k (Note 6) f = 100kHz, RL = 2k VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 2k Per Amplifier 15V 15V 5V 5V 15V 15V 5V 5V 15V 5V 15V 15V 5V 15V 5V 15V 5V 15V 5V 15V 5V
q q q q q q q q q q q q q q q q q q q q q
VOUT
Maximum Output Swing
IOUT ISC SR GBW
Maximum Output Current Output Short-Circuit Current Slew Rate Gain Bandwidth Product Channel Separation
IS VOS IB - IB + CMRR PSRR
Supply Current Input Offset Voltage Match Inverting Input Bias Current Match Noninverting Input Bias Current Match Common Mode Rejection Match Power Supply Rejection Match
6.5 6.3 600 600 38 118 91 91 92
mA mA V V nA nA dB dB dB
5V to 15V q 5V to 15V q VCM = 12.5V (Note 9) VCM = 2.5V (Note 9) VS = 4.5V to 15V (Note 9) 15V 5V
q q q
The q denotes the specifications which apply over the temperature range - 40C TA 85C, VCM = 0V unless otherwise noted. (Note 5)
SYMBOL PARAMETER VOS VOS/T IOS IOS/T IB - IB -/T IB + VCM Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Offset Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Noninverting Input Bias Current Input Voltage Range (Positive) Input Voltage Range (Negative) (Note 8) (Note 8) (Note 8) CONDITIONS VSUPPLY 15V 5V
q q
MIN
TYP
MAX 500 500
UNITS V V V/C nA pA/C nA pA/C nA V V
5V to 15V q 5V to 15V q 5V to 15V q 5V to 15V q 5V to 15V 15V 5V 15V 5V
q
1 120
4 120 40
80 80 12.5 2.5 -12.5 -2.5
5V to 15V q
q q q q
V V
4
LT1469
The q denotes the specifications which apply over the temperature range - 40C TA 85C, VCM = 0V unless otherwise noted. (Note 5)
SYMBOL PARAMETER CMRR Common Mode Rejection Ratio Minimum Supply Voltage PSRR AVOL Power Supply Rejection Ratio Large-Signal Voltage Gain CONDITIONS VCM = 12.5V VCM = 2.5V Guaranteed by PSRR VS = 4.5V to 15V VOUT = 12,5V, RL = 10k VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 10k VOUT = 2.5V, RL = 2k RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive VOUT = 12.5V, 1mV Overdrive VOUT = 2.5V, 1mV Overdrive VOUT = 0V, 0.2V Overdrive (Note 3) AV = -10, RL = 2k (Note 6) f = 100kHz, RL = 2k VOUT = 12.5V, RL = 2k VOUT = 2.5V, RL = 2k Per Amplifier 15V 15V 5V 5V 15V 15V 5V 5V 15V 5V 15V 15V 5V 15V 5V 15V 5V 15V 5V 15V 5V VSUPPLY 15V 5V
q q q q q q q q q q q q q q q q q q q q q q q q q
ELECTRICAL CHARACTERISTICS
MIN 92 92
TYP
MAX
UNITS dB dB
4.5 93 75 75 75 75 12.8 12.6 2.8 2.6 7 7 12 9 6 45 40 96 96 7 6.8 800 800 78 158 89 89 90
V dB V/mV V/mV V/mV V/mV V V V V mA mA mA V/s V/s MHz MHz dB dB mA mA V V nA nA dB dB dB
VOUT
Maximum Output Swing
IOUT ISC SR GBW
Maximum Output Current Output Short-Circuit Current Slew Rate Gain Bandwidth Product Channel Separation
IS VOS IB - IB + CMRR PSRR
Supply Current Input Offset Voltage Match Inverting Input Bias Current Match Noninverting Input Bias Current Match Common Mode Rejection Match Power Supply Rejection Match
5V to 15V q 5V to 15V q VCM = 12.5V (Note 9) VCM = 2.5V (Note 9) VS = 4.5V to 15V (Note 9) 15V 5V
q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes and two 100 series resistors. If the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA. Input voltages outside the supplies will be clamped by ESD protection devices and input currents should also be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note 4: The LT1469C and LT1469I are guaranteed functional over the operating temperature range of - 40C to 85C. Note 5: The LT1469C is guaranteed to meet specified performance from 0C to 70C and is designed, characterized and expected to meet specified
performance from - 40C to 85C but is not tested or QA sampled at these temperatures. The LT1469I is guaranteed to meet specified performance from - 40C to 85C. Note 6: Slew rate is measured between 8V on the output with 12V swing for 15V supplies and 2V on the output with 3V swing for 5V supplies. Note 7: Full-power bandwidth is calculated from the slew rate. FPBW = SR/2VP. Note 8: This parameter is not 100% tested. Note 9: CMRR and PSRR are defined as follows: 1) CMRR and PSRR are measured in V/V on each amplifier; 2) the difference between the two sides is calculated in V/V; 3) the result is converted to dB.
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LT1469
APPLICATIO S I FOR ATIO
Layout and Passive Components The LT1469 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example, fast settling time) use a ground plane, short lead lengths and RF quality bypass capacitors (0.01F to 0.1F) in parallel with low ESR bypass capacitors (1F to 10F tantalum). For best DC performance, use "star" grounding techniques, equalize input trace lengths and minimize leakage (i.e., 1.5G of leakage between an input and a 15V supply will generate 10nA--equal to the maximum IB - specification). Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below).
RG CIN VIN
Figure 1. Nulling Input Capacitance
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Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short and the two input leads should be as close together as possible and maintained at the same temperature. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. For feedback resistors greater than 2k, a feedback capacitor of value CF > RG * CIN/RF should be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, CF should be greater than or equal to CIN. An example would be a DAC I-to-V converter as shown on the back page of the data sheet where the DAC can have many tens of picofarads of output capacitance. Another example would be a gain of -1 with 5k resistors; a 5pF to 10pF capacitor should be added across the feedback resistor.
CF RF
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1469 F01
LT1469
APPLICATIO S I FOR ATIO
Input Considerations Each input of the LT1469 is protected with a 100 series resistor and back-to-back diodes across the bases of the input devices. If large differential input voltages are anticipated, limit the input current to less than 10mA with an external series resistor. Each input also has two ESD clamp diodes--one to each supply. If an input is driven beyond the supply, limit the current with an external resistor to less than 10mA. The LT1469 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as I-to-V converters. The noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. As the input offset current can be greater than either input current, the use of balanced source resistance is NOT recommended as it actually degrades DC accuracy and also increases noise.
+IN
R1 100 Q1
Figure 2. Input Stage Protection
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The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. The LT1469 inputs can be driven to the negative supply and to within 0.5V of the positive supply without phase reversal. As the input moves closer than 0.5V to the positive supply, the output reverses phase. Total Input Noise The total input noise of the LT1469 is optimized for a source resistance between 1k and 20k. Within this range, the total input noise is dominated by the noise of the source resistance itself. When the source resistance is below 1k, voltage noise of the amplifier dominates. When the source resistance is above 20k, the input noise current is the dominant contributor.
R1 Q2 100 -IN
1469 F02
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LT1469
APPLICATIO S I FOR ATIO
Capacitive Loading The LT1469 drives capacitive loads of up to 100pF in unitygain and 300pF in a gain of -1. When there is a need to drive a larger capacitive load, a small series resistor should be inserted between the output and the load. In addition, a capacitor should be added between the output and the inverting input as shown in Figure 3. Settling Time The LT1469 is a single stage amplifier with an optimal thermal layout that leads to outstanding settling performance. Measuring settling, even at the 12-bit level is very challenging, and at the 16-bit level requires a great deal of subtlety and expertise. Fortunately, there are two excellent Linear Technology reference sources for settling measurements--Application Notes 47 and 74. Appendix B of AN47 is a vital primer on 12-bit settling measurements and AN74 extends the state-of-the-art while concentrating on settling time with a 16-bit current output DAC input.
RG
-
1/2 LT1469 VIN
+
Figure 3. Driving Capacitive Loads
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The settling of the DAC I-to-V converter on the back page was measured using the exact methods of AN74. The optimum nulling of the DAC output capacitance requires 20pF across the 6k feedback resistor. The theoretical limit for 16-bit settling is 11.1 times this RC time constant or 1.33s. The actual settling time is 1.7s at the output of the LT1469. The LT1469 is the fastest Linear Technology amplifier in this application. The RC output noise filter adds a slight settling time delay of 100ns but reduces the noise bandwidth to 1.6MHz which increases the output resolution for 16-bit accuracy.
RF RO (1 + RF/RG)/(2 * CL * 5MHz) RF 10RO CF = (2RO/RF)CL CF RO VOUT CL
1469 F03
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LT1469
SI PLIFIED SCHE ATIC W
I3 V-
1469 SS
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V+ I1 I2 I5 Q10 Q8 + IN Q1 Q2 - IN Q5 Q6 Q7 Q3 Q4 BIAS C Q11 Q9 OUT
I4
I6
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LT1469
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.255 0.015* (6.477 0.381)
1 0.300 - 0.325 (7.620 - 8.255)
2
3
4 0.130 0.005 (3.302 0.127)
0.045 - 0.065 (1.143 - 1.651)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
N8 1098
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
0.100 (2.54) BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
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LT1469
PACKAGE DESCRIPTIO
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 (0.406 - 1.270)
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Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.050 (1.270) BSC
SO8 1298
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LT1469
TYPICAL APPLICATIO
16-Bit DAC I-to-V Converter and Reference Inverter for Bipolar Output Swing (VOUT = -10V to 10V)
REF
16 BITS DAC INPUTS
RELATED PARTS
PART NUMBER LT1167 LT1468 LTC1595/LTC1596 LTC1597 LT1604 LTC1605 DESCRIPTION Precision Instrumentation Amplifier Single 90MHz, 22V/s, 16-Bit Accurate Op Amp 16-Bit Serial Multiplying IOUT DAC 16-Bit Parallel Multiplying IOUT DAC 16-Bit, 333ksps Sampling ADC Single 5V, 16-Bit, 100ksps Sampling ADC COMMENTS Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity 75V Max VOS, Single Version of LT1469 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors 2.5V Input, SINAD = 90dB, THD = -100dB Low Power, 10V Inputs, Parallel/Byte Interface
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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1/2 LT1469
-
15pF
20pF
LTC1597
-
1/2 LT1469
2k VOUT 50pF
1469 TA03
+
1469i LT/TP 0200 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2000

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